Masahide Takada

Publication Activity (10 Years)

Years Active: 1990-1996
Publications (10 Years): 0

Publications

Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki
A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. IEEE J. Solid State Circuits 31 (11) (1996)
Hiraki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihira Hayashi, Yukihiko Maejima, Kazushi Amanuma, Nobuhira Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada
A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme. IEEE J. Solid State Circuits 31 (11) (1996)
Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki
A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump. IEEE J. Solid State Circuits 31 (1) (1996)
Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Tom Yamazaki
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. IEEE J. Solid State Circuits 30 (11) (1995)
Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki
A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. IEEE J. Solid State Circuits 29 (11) (1994)
Masao Fukuma, Hiroshi Furuta, Masahide Takada
Memory LSI reliability. Proc. IEEE 81 (5) (1993)
Hiroki Koike, Toshio Takeshima, Masahide Takada
A BIST scheme using microprogram ROM for large capacity memories. ITC (1990)