Tohru Kimura

Publication Activity (10 Years)

Years Active: 1994-2008
Publications (10 Years): 0

Publications

Tohru Kimura, Hitoshi Yano, Yuuichi Aoki, Nobuhide Yoshida, Jun Noda, Teruki Sukenari, Yusuke Konishi, Toshiyasu Nakao, Akitake Mitsuhashi, Daigo Taguchi
A Wireless Dual-Link System for Sensor Network Applications. ISSCC (2008)
Yoshihiro Fujita, Nobuyuki Yamashita, Tohru Kimura, Kazuyuki Nakamura, Shin'ichiro Okazaki
A 3.84 gips integrated memory array processor. Systems and Computers in Japan 27 (3) (1996)
Hiraki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihira Hayashi, Yukihiko Maejima, Kazushi Amanuma, Nobuhira Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada
A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme. IEEE J. Solid State Circuits 31 (11) (1996)
Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. IEEE J. Solid State Circuits 30 (6) (1995)
Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. IEEE J. Solid State Circuits 29 (11) (1994)
Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki
A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator. IEEE J. Solid State Circuits 29 (11) (1994)