Shin'ichiro Okazaki

Publication Activity (10 Years)

Years Active: 1992-2012
Publications (10 Years): 0

Top Venues

Publications

Hanno Lieske, Shorin Kyo, Shouhei Nomoto, Sunao Torii, Yuki Kobayashi, Yasuyuki Ninomiya, Shin'ichiro Okazaki
Efficient data transfer operations for a SIMD processor array system. ICASSP (2012)
Shouhei Nomoto, Shorin Kyo, Shin'ichiro Okazaki
A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems. A-SSCC (2011)
Shorin Kyo, Shin'ichiro Okazaki
IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements. J. Signal Process. Syst. 62 (1) (2011)
Shouhei Nomoto, Shorin Kyo, Shin'ichiro Okazaki
Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Shorin Kyo, Shouhei Nomoto, Takuya Koga, Hanno Lieske, Shin'ichiro Okazaki
IMAPCAR2: A dynamic SIMD/MIMD mode switching processor for embedded systems. Hot Chips Symposium (2009)
Shorin Kyo, Shouhei Nomoto, Shin'ichiro Okazaki
Mapping schemes of image recognition tasks onto highly parallel SIMD/MIMD processors. ICDSC (2009)
Shorin Kyo, Shin'ichiro Okazaki
In-vehicle vision processors for driver assistance systems. ASP-DAC (2008)
Kazuyuki Sakurai, Shorin Kyo, Shin'ichiro Okazaki
Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor. IEICE Trans. Inf. Syst. (7) (2008)
Shorin Kyo, Takuya Koga, Hanno Lieske, Shouhei Nomoto, Shin'ichiro Okazaki
A low-cost mixed-mode parallel processor architecture for embedded systems. ICS (2007)
Kazuyuki Sakurai, Shorin Kyo, Shin'ichiro Okazaki
Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor. MVA (2007)
Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai
An Integrated Memory Array Processor for Embedded Image Recognition Systems. IEEE Trans. Computers 56 (5) (2007)
Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems. ISCA (2005)
Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda
A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications. IEICE Trans. Inf. Syst. (1) (2004)
Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda
A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements. IEEE J. Solid State Circuits 38 (11) (2003)
Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki
IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements. ICIP (3) (2001)
Yoshihiro Fujita, Nobuyuki Yamashita, Tohru Kimura, Kazuyuki Nakamura, Shin'ichiro Okazaki
A 3.84 gips integrated memory array processor. Systems and Computers in Japan 27 (3) (1996)
Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki
An integrated memory array processor with a synchronous-DRAM interface for real-time vision applications. ICPR (1996)
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro Okazaki
IMAP-VISION: An SIMD Processor with High-Speed On-chip Memory and Large Capacity External Memory. MVA (1996)
Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita
A compact real-time vision system using integrated memory array processor architecture. IEEE Trans. Circuits Syst. Video Technol. 5 (5) (1995)
Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. IEEE J. Solid State Circuits 30 (6) (1995)
Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manabe, Shin'ichiro Okazaki, Kazuyuki Nakamura, Masakazu Yamashina
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. IEEE J. Solid State Circuits 29 (11) (1994)
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro Okazaki
A real-time vision system using an integrated memory array processor prototype. Mach. Vis. Appl. 7 (4) (1994)
Shin'ichiro Okazaki, Yoshihiro Fujita, Nobuyuki Yamashita
A Compact 30GIPS Real-Time Vision System RVS-2. MVA (1994)
Sholin Kyo, Shin'ichiro Okazaki, Masanori Mizoguchi
Dataflow Graph Optimization for Dataflow Architectures - A Dataflow Optimizing Compiler. ICPP (2) (1993)
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro Okazaki
A Real-Time Vision System Using Integrated Memory Array Processor Prototype LSI. MVA (1992)
Yoshihiro Fujita, Nobuyuki Yamashita, Shin'ichiro Okazaki
Imap: Integrated Memory Array Processor. J. Circuits Syst. Comput. 2 (3) (1992)