A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM.
Nobuyuki YamashitaTohru KimuraYoshihiro FujitaYoshiharu AimotoTakashi ManabeShin'ichiro OkazakiKazuyuki NakamuraMasakazu YamashinaPublished in: IEEE J. Solid State Circuits (1994)
Keyphrases
- processing elements
- array processor
- scan line
- linear array
- random access
- massively parallel
- associative memory
- image processing algorithms
- parallel processors
- hardware architecture
- semantic network
- parallel computers
- parallel architectures
- parallel architecture
- hardware implementation
- power consumption
- single instruction multiple data
- image processing
- high performance computing
- dynamic programming
- computer architecture
- parallel processing
- machine learning