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A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture.
Kouichi Yamaguchi
Muneo Fukaishi
Takehiko Sakamoto
Naoto Akiyama
Kazuyuki Nakamura
Published in:
IEEE J. Solid State Circuits (2001)
Keyphrases
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feedback loop
feedback loops
high speed
finite element model
steady state
fuzzy cognitive maps
fourier series
real time
management system
power consumption
scalable distributed
evolutionary algorithm
software architecture
multiprocessor architecture