Mai Nozawa

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 4

Top Topics

Transaction Processing Systems

Fine Granularity

Data Repositories

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEEE J. Solid State Circuits

Publications

Fumihiko Tachibana, Huy Cu Ngo, Go Urakawa, Takashi Toi, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Junji Wadatsumi, Hiroyuki Kobayashi, Jun Deguchi
A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (5) (2024)
Fumihiko Tachibana, Huy Cu Ngo, Go Urakawa, Takashi Toi, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Junji Wadatsumi, Hiroyuki Kobayashi, Jun Deguchi
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR. ESSCIRC (2022)
Takashi Toi, Junji Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu, Yuji Satoh, Makoto Morimoto, Rui Ito, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Go Urakawa, Jun Deguchi, Ryuichi Fujimoto
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. IEEE J. Solid State Circuits 57 (5) (2022)
Takashi Toi, Junji Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu, Yuji Satoh, Makoto Morimoto, Rui Ito, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Go Urakawa, Jun Deguchi
A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. ISSCC (2019)
Masanori Furuta, Mai Nozawa, Tetsuro Itakura
A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique. IEEE J. Solid State Circuits 46 (6) (2011)
Masanori Furuta, Mai Nozawa, Tetsuro Itakura
8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS. ISSCC (2010)