Ryuichi Fujimoto

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 16

Top Topics

Top Venues

IEICE Trans. Electron.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Ryuichi Fujimoto
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (5) (2024)
Takashi Toi, Junji Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu, Yuji Satoh, Makoto Morimoto, Rui Ito, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Go Urakawa, Jun Deguchi, Ryuichi Fujimoto
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. IEEE J. Solid State Circuits 57 (5) (2022)
Kengo Nakata, Daisuke Miyashita, Asuka Maki, Fumihiko Tachibana, Shinichi Sasaki, Jun Deguchi, Ryuichi Fujimoto
Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN. AICAS (2021)
Go Urakawa, Hiroyuki Kobayashi, Jun Deguchi, Ryuichi Fujimoto
A Noise-Canceling Charge Pump for Area Efficient PLL Design. IEICE Trans. Electron. (10) (2021)
Kengo Nakata, Daisuke Miyashita, Jun Deguchi, Ryuichi Fujimoto
Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization. ISCAS (2021)
Asuka Maki, Daisuke Miyashita, Shinichi Sasaki, Kengo Nakata, Fumihiko Tachibana, Tomoya Suzuki, Jun Deguchi, Ryuichi Fujimoto
Weight Compression MAC Accelerator for Effective Inference of Deep Learning. IEICE Trans. Electron. (10) (2020)
Yuta Tsubouchi, Daisuke Miyashita, Takashi Toi, Yuji Satoh, Fumihiko Tachibana, Junji Wadatsumi, Makoto Morimoto, Ryuichi Fujimoto, Jun Deguchi
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems. IEEE J. Solid State Circuits 54 (4) (2019)
Koichi Ito, Ryuichi Fujimoto, Tzu-Wei Huang, Hwann-Tzong Chen, Kai Wu, Kazunori Sato, Yasuyuki Taki, Hiroshi Fukuda, Takafumi Aoki
Performance Evaluation of Age Estimation from T1-Weighted Images Using Brain Local Features and CNN. EMBC (2018)
Atsushi Shirane, Shusuke Kawai, Hiromitsu Aoyama, Rui Ito, Toshiya Mitomo, Hiroyuki Kobayashi, Hiroshi Yoshida, Hideaki Majima, Ryuichi Fujimoto, Hiroshi Tsurumi
A low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN. ESSCIRC (2017)
Yosuke Ogasawara, Ryuichi Fujimoto, Tsuneo Suzuki, Kenichi Sami
An 18 µW Spur Cancelled Clock Generator for Recovering Receiver Sensitivity in Wireless SoCs. IEICE Trans. Electron. (6) (2017)
Tzu-Wei Huang, Hwann-Tzong Chen, Ryuichi Fujimoto, Koichi Ito, Kai Wu, Kazunori Sato, Yasuyuki Taki, Hiroshi Fukuda, Takafumi Aoki
Age estimation from brain MRI images using deep learning. ISBI (2017)
Ryuichi Fujimoto, Koichi Ito, Kai Wu, Kazunori Sato, Yasuyuki Taki, Hiroshi Fukuda, Takafumi Aoki
Brain age estimation from T1-weighted images using effective local features. EMBC (2017)
Manabu Yamada, Nam Binh Tran, Takayuki Miyazaki, Yoshiaki Yoshihara, Ryuichi Fujimoto
All-digital single-inductor multiple-output DC-DC converter with over 65.3% efficiency in 1 uW to 50 mW load range and 86.3% peak efficiency. A-SSCC (2016)
Ryuichi Fujimoto, Chihiro Kondo, Koichi Ito, Kai Wu, Kazunori Sato, Yasuyuki Taki, Hiroshi Fukuda, Takafumi Aoki
Age estimation using effective brain local features from T1-weighted images. EMBC (2016)
Yosuke Ogasawara, Hiroki Sakurai, Ryuichi Fujimoto, Kenichi Sami
An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs. VLSI Circuits (2016)
Ryuichi Fujimoto
Analog and Digital Collaborative Design Techniques for Wireless SoCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2016)
Yoshiaki Yoshihara, Hideaki Majima, Ryuichi Fujimoto
A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control. ESSCIRC (2014)
Kenichi Agawa, Ichiro Seto, Akihiko Happoya, Yoshihiro Iida, Yusuke Imaizumi, Motochika Okano, Daigo Suzuki, Yuichi Sato, Masaomi Iwanaga, Kazumi Sato, Satoshi Arai, Noriaki Uchida, Koji Ryugo, Daisuke Miyashita, Ryuichi Fujimoto, Yasuo Unekawa
3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver. RWS (2014)
Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Ichiro Seto, Ryuichi Fujimoto, Yasuo Unekawa
SoC in 65 nm CMOS. IEICE Trans. Electron. (6) (2013)
Minoru Fujishima, Mizuki Motoyoshi, Kosuke Katayama, Kyoya Takano, Naoko Ono, Ryuichi Fujimoto
98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits. IEEE J. Solid State Circuits 48 (10) (2013)
Ryuichi Fujimoto, Mizuki Motoyoshi, Kyoya Takano, Minoru Fujishima
A 120 GHz/140 GHz Dual-Channel OOK Receiver Using 65 nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2013)
Kyoya Takano, Ryuichi Fujimoto, Mizuki Motoyoshi, Kosuke Katayama, Minoru Fujishima
14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. RWS (2013)
Ryuichi Fujimoto
Foreword. IEICE Trans. Electron. (6) (2013)
Kosuke Katayama, Mizuki Motoyoshi, Kyoya Takano, Ryuichi Fujimoto, Minoru Fujishima
Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit. IEICE Trans. Electron. (6) (2012)
Naoko Ono, Mizuki Motoyoshi, Kyoya Takano, Kosuke Katayama, Ryuichi Fujimoto, Minoru Fujishima
135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS. VLSIC (2012)
Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Masaomi Iwanaga, Yosuke Ogasawara, Tomohiko Ito, Daisuke Kurose, Naotaka Koide, Toru Hashimoto, Hiroki Sakurai, Takafumi Yamaji, Takashi Kurihara, Kazumi Sato, Ichiro Seto, Hiroshi Yoshida, Ryuichi Fujimoto, Yasuo Unekawa
A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. VLSIC (2012)
Daisuke Miyashita, Hiroyuki Kobayashi, Jun Deguchi, Shouhei Kousai, Mototsugu Hamada, Ryuichi Fujimoto
A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter. IEICE Trans. Electron. (6) (2012)
Ryuichi Fujimoto, Mizuki Motoyoshi, Kyoya Takano, Uroschanit Yodprasit, Minoru Fujishima
A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology. IEICE Trans. Electron. (7) (2012)
Yoshimitsu Takamatsu, Ryuichi Fujimoto, Tsuyoshi Sekine, Takaya Yasuda, Mitsumasa Nakamura, Takuya Hirakawa, Masato Ishii, Motohiko Hayashi, Hiroya Ito, Yoko Wada, Teruo Imayama, Tatsuro Oomoto, Yosuke Ogasawara, Masaki Nishikawa, Yoshihiro Yoshida, Kenji Yoshioka, Shigehito Saigusa, Hiroshi Yoshida, Nobuyuki Itoh
A Single-Chip RF Tuner/OFDM Demodulator for Mobile Digital TV Application. IEICE Trans. Electron. (4) (2011)
Kyoya Takano, Ryuichi Fujimoto, Kosuke Katayama, Mizuki Motoyoshi, Minoru Fujishima
Analysis of De-Embedding Error Cancellation in Cascade Circuit Design. IEICE Trans. Electron. (10) (2011)
Mizuki Motoyoshi, Ryuichi Fujimoto, Kyoya Takano, Minoru Fujishima
140GHz CMOS amplifier with group delay variation of 10.2ps and 0.1dB bandwidth of 12GHz. IEICE Electron. Express 8 (14) (2011)
Ryuichi Fujimoto, Kyoya Takano, Mizuki Motoyoshi, Uroschanit Yodprasit, Minoru Fujishima
Device Modeling Techniques for High-Frequency Circuits Design Using Bond-Based Design at over 100 GHz. IEICE Trans. Electron. (4) (2011)
Hiroaki Hoshino, Ryoichi Tachibana, Toshiya Mitomo, Naoko Ono, Yoshiaki Yoshihara, Ryuichi Fujimoto
A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS. IEICE Trans. Electron. (6) (2009)
Tsuyoshi Sekine, Ryuichi Fujimoto, Yoshimitsu Takamatsu, Mitsumasa Nakamura, Takuya Hirakawa, Masato Ishii, Takaya Yasuda, Motohiko Hayashi, H. Itoh, Yoko Wada, Teruo Imayama, Tatsuro Oomoto, Yosuke Ogasawara, Shigehito Saigusa, M. Yano, Masaki Nishikawa, Hiroshi Yoshida, Yoshihiro Yoshida, Kenji Yoshioka, Nobuyuki Itoh
A single-chip RF tuner / OFDM demodulator for mobile digital TV application. ESSCIRC (2009)
Toshiya Mitomo, Ryuichi Fujimoto, Naoko Ono, Ryoichi Tachibana, Hiroaki Hoshino, Yoshiaki Yoshihara, Yukako Tsutsumi, Ichiro Seto
A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer. IEEE J. Solid State Circuits 43 (4) (2008)
Ryuichi Fujimoto, Gaku Takemura, Masato Ishii, Takehiko Toyoda, Hiroshi Tsurumi
A Low-Noise Amplifier for WCDMA Terminal with High Tolerance for Leakage Signal from Transmitter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Toshiya Mitomo, Osamu Watanabe, Ryuichi Fujimoto, Shunji Kawaguchi
A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage. IEICE Trans. Electron. (6) (2007)
Hiroaki Hoshino, Ryoichi Tachibana, Toshiya Mitomo, Naoko Ono, Yoshiaki Yoshihara, Ryuichi Fujimoto
A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS. ESSCIRC (2007)
Toshiya Mitomo, Osamu Watanabe, Ryuichi Fujimoto, Shunji Kawaguchi
A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage. CICC (2006)
Toshiya Mitomo, Osamu Watanabe, Shoji Otaka, Ryuichi Fujimoto, Shunji Kawaguchi
A Low LO Leakage and Low Power LO Buffer for Direct-Conversion Quadrature Demodulator. IEICE Trans. Electron. (6) (2005)
Hiroshi Yoshida, Takehiko Toyoda, Makoto Arai, Ryuichi Fujimoto, Toshiya Mitomo, Masato Ishii, Rui Ito, Tadashi Arai, Tetsuro Itakura, Hiroshi Tsurumi
A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA. IEICE Trans. Electron. (6) (2005)
Ryuichi Fujimoto, Kenji Kojima, Shoji Otaka
A 7-GHz 1.8-dB NF CMOS low-noise amplifier. IEEE J. Solid State Circuits 37 (7) (2002)
Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Akira Yasuda, Ryuichi Fujimoto, Tadashi Arai, Hideyuki Kokatsu
A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC. IEEE J. Solid State Circuits 34 (8) (1999)
Shoji Otaka, Takafumi Yamaji, Ryuichi Fujimoto, Chikau Takahashi, Hiroshi Tanimoto
A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment. IEEE J. Solid State Circuits 31 (1) (1996)