A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.
Takashi ToiJunji WadatsumiHiroyuki KobayashiYutaka ShimizuYuji SatohMakoto MorimotoRui ItoMitsuyuki AshidaYuta TsubouchiMai NozawaGo UrakawaJun DeguchiRyuichi FujimotoPublished in: IEEE J. Solid State Circuits (2022)