SoC in 65 nm CMOS.

Daisuke Miyashita Kenichi Agawa Hirotsugu Kajihara Kenichi Sami Ichiro Seto Ryuichi Fujimoto Yasuo Unekawa

Published in: IEICE Trans. Electron. (2013)

Keyphrases

low power
cmos technology
nm technology
power consumption
silicon on insulator
high speed
low cost
metal oxide semiconductor
low voltage
single chip
digital signal processing
vlsi circuits
image sensor
delay insensitive
hardware and software
power dissipation
databases
case study
metal oxide
information systems