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Hiroki Sakurai
Publication Activity (10 Years)
Years Active: 2005-2016
Publications (10 Years): 1
Top Topics
Privacy Protection
Wireless Lan
Speaker Diarization
Sensitivity Analysis
Top Venues
VLSIC
VLSI Circuits
IIH-MSP
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Publications
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Yosuke Ogasawara
,
Hiroki Sakurai
,
Ryuichi Fujimoto
,
Kenichi Sami
An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs.
VLSI Circuits
(2016)
Kazuhiro Kondo
,
Hiroki Sakurai
Gender-Dependent Babble Maskers Created from Multi-speaker Speech for Speech Privacy Protection.
IIH-MSP
(2014)
Daisuke Miyashita
,
Kenichi Agawa
,
Hirotsugu Kajihara
,
Kenichi Sami
,
Masaomi Iwanaga
,
Yosuke Ogasawara
,
Tomohiko Ito
,
Daisuke Kurose
,
Naotaka Koide
,
Toru Hashimoto
,
Hiroki Sakurai
,
Takafumi Yamaji
,
Takashi Kurihara
,
Kazumi Sato
,
Ichiro Seto
,
Hiroshi Yoshida
,
Ryuichi Fujimoto
,
Yasuo Unekawa
A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS.
VLSIC
(2012)
Hiroki Sakurai
,
Yuka Kobayashi
,
Toshiya Mitomo
,
Osamu Watanabe
,
Shoji Otaka
A 1.5GHz-modulation-range 10ms-modulation-period 180kHzrms-frequency-error 26MHz-reference mixed-mode FMCW synthesizer for mm-wave radar application.
ISSCC
(2011)
Kiyokazu Umimura
,
Hiroki Sakurai
,
Yasuhiro Sugimoto
A CMOS Current-mode DC-DC converter with input and output voltage-independent stability and frequency characteristics utilizing a quadratic slope compensation scheme.
ESSCIRC
(2007)
Hiroki Sakurai
,
Shigeto Tanaka
,
Yasuhiro Sugimoto
A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(10) (2007)
Hiroki Sakurai
,
Yasuhiro Sugimoto
Amplification Scheme.
IEICE Trans. Electron.
(2) (2007)
Hiroki Sakurai
,
Yasuhiro Sugimoto
Analysis and Design of a Current-Mode PWM Buck Converter Adopting the Output-Voltage Independent Second-Order Slope Compensation Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(2) (2005)