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A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture.
Hiroki Sakurai
Shigeto Tanaka
Yasuhiro Sugimoto
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2007)
Keyphrases
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analog to digital converter
random access memory
image sensor
instruction set architecture
low cost
data flow
real time
error rate
flip flops
power consumption
error bounds
design considerations
parallel architecture
cmos technology
xilinx virtex
cmos image sensor
high speed