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Low-Power Design of 10-bit 80-MSPS Pipeline ADCs.
Tomohiko Ito
Daisuke Kurose
Takeshi Ueno
Takafumi Yamaji
Tetsuro Itakura
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2006)
Keyphrases
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low power
low power consumption
power consumption
high speed
low cost
single chip
vlsi architecture
logic circuits
digital signal processing
design process
power reduction
gate array
power dissipation
nm technology
cmos technology
image sensor
wireless transmission
vlsi circuits
design methodology