A 2-GHz Down-Converter with 3-dB Bandwidth of 600 MHz Using LO Signal Suppressing Output Buffer.
Osamu WatanabeTakafumi YamajiTetsuro ItakuraIchiro HattoriPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2002)
Keyphrases
- radiation pattern
- phased array
- clock frequency
- frequency band
- noise elimination
- radio frequency
- high frequency
- noise ratio
- high speed
- buffer size
- power consumption
- learning objects
- low frequency
- signal processing
- transfer function
- frequency domain
- parallel computing
- field programmable gate array
- parallel architecture
- blocking probability
- low power
- parallel processing