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A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS.

Akihide SaiYuka KobayashiShigehito SaigusaOsamu WatanabeTetsuro Itakura
Published in: ISSCC (2012)
Keyphrases
  • cmos technology
  • low cost
  • high speed
  • power consumption
  • neural network
  • image sequences
  • low power
  • information systems
  • packet loss
  • circuit design
  • power supply
  • vlsi circuits
  • nm technology