A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter.
Tatsuji MatsuuraTakashi NaraTatsuya KomatsuEiki ImaizumiToshihiro MatsutsuruRyutaro HoritaHaruto KatsuShintaro SuzumuraKazuo SatoPublished in: IEEE J. Solid State Circuits (1998)
Keyphrases
- analog vlsi
- analog to digital converter
- low voltage
- high speed
- cmos technology
- cmos image sensor
- mixed signal
- circuit design
- multi channel
- random access memory
- low cost
- latent semantic indexing
- single chip
- low power
- image sensor
- chip design
- dynamic range
- parallel processing
- power dissipation
- metal oxide semiconductor
- transfer function
- vlsi architecture
- solid state
- data conversion
- vector space
- focal plane
- text retrieval
- nm technology
- ultra low power
- design considerations
- power consumption
- parallel architecture
- steady state
- low power consumption
- physical design
- high voltage
- channel coding
- cellular networks
- high density
- wireless sensor networks