A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.
Hiroki MiyaokaFutoshi TerasawaMasahiro KudoHideki KanoAtsushi MatsudaNoriaki ShiraiShigeaki KawaiTakayuki ShibasakiTakumi DanjoYuuki OgataYasufumi SakaiHisakatsu YamaguchiToshihiko MoriYoichi KoyanagiHirotaka TamuraYutaka IdeKazuhiro TerashimaHirohito HigashiTomokazu HiguchiNaoaki NakaPublished in: VLSI Circuits (2016)