A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.
Takayuki ShibasakiWin ChaivipasYanfei ChenYoshiyasu DoiTakayuki HamadaHideki TakauchiToshihiko MoriYoichi KoyanagiHirotaka TamuraPublished in: VLSIC (2014)
Keyphrases
- decision feedback
- high speed
- cmos technology
- silicon on insulator
- metal oxide semiconductor
- nm technology
- low power
- back end
- error propagation
- power consumption
- soft decision
- multipath
- power supply
- low cost
- low voltage
- delay insensitive
- bit error rate
- analog vlsi
- vlsi circuits
- ibm power processor
- image sensor
- end to end