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A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.
Takayuki Shibasaki
Win Chaivipas
Yanfei Chen
Yoshiyasu Doi
Takayuki Hamada
Hideki Takauchi
Toshihiko Mori
Yoichi Koyanagi
Hirotaka Tamura
Published in:
VLSIC (2014)
Keyphrases
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decision feedback
high speed
cmos technology
silicon on insulator
metal oxide semiconductor
nm technology
low power
back end
error propagation
power consumption
soft decision
multipath
power supply
low cost
low voltage
delay insensitive
bit error rate
analog vlsi
vlsi circuits
ibm power processor
image sensor
end to end