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A ferroelectric memory-based secure dynamically programmable gate array.
Shoichi Masui
Tsuzumi Ninomiya
Michiya Oura
Wataru Yokozeki
Kenji Mukaida
Shoichiro Kawashima
Published in:
IEEE J. Solid State Circuits (2003)
Keyphrases
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gate array
low power
low cost
single chip
logic circuits
general purpose
security issues
key management
high speed
power consumption
standard model
key distribution
memory based learning
cryptographic protocols
identity management
signal processor