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A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.

Takushi HashidaYasumoto TomitaYuuki OgataKosuke SuzukiShigeto SuzukiTakanori NakaoYuji TeraoSatofumi HondaSota SakabayashiRyuichi NishiyamaAkihiko KonmotoYoshitomo OzekiHiroyuki AdachiHisakatsu YamaguchiYoichi KoyanagiHirotaka Tamura
Published in: VLSIC (2014)
Keyphrases
  • power consumption
  • nm technology
  • low power
  • high speed
  • power supply
  • cmos technology
  • hd video
  • low cost
  • real time
  • probability distribution
  • solid state
  • fpga device
  • ultra low power