An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors.
Tetsutaro HashimotoYukihito KawabeMichiharu HaraYasushi KakimuraKunihiko TajiriShinichiro ShirotaRyuichi NishiyamaHitoshi SakuraiHiroshi OkanoYasumoto TomitaSugio SatohHideo YamashitaPublished in: IEEE J. Solid State Circuits (2018)