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A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.

Nikola NedovicAnders KristenssonSamir ParikhSubodh M. ReddyScott McLeodNestoras TzartzanisKouichi KandaTakuji YamamotoSatoshi MatsubaraMasaya KibuneYoshiyasu DoiSatoshi IdeYukito TsunodaTetsuji YamabanaTakayuki ShibasakiYasumoto TomitaTakayuki HamadaMariko SugawaraTadashi IkeuchiNaoki KuwataHirotaka TamuraJunji OgawaWilliam W. Walker
Published in: IEEE J. Solid State Circuits (2010)
Keyphrases
  • high speed
  • low cost
  • small number
  • data sets
  • neural network
  • genetic algorithm
  • learning algorithm
  • decision trees
  • low power
  • analog vlsi