Nestoras Tzartzanis

Publication Activity (10 Years)

Years Active: 1991-2010
Publications (10 Years): 0

Publications

Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. IEEE J. Solid State Circuits 45 (10) (2010)
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. ISSCC (2009)
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. IEEE J. Solid State Circuits 44 (12) (2009)
Yolin Lih, Nestoras Tzartzanis, William W. Walker
A Leakage Current Replica Keeper for Dynamic Circuits. IEEE J. Solid State Circuits 42 (1) (2007)
Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. ISSCC (2007)
Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX. IEEE J. Solid State Circuits 42 (12) (2007)
Nestoras Tzartzanis, William W. Walker
A Reversible Poly-Phase Distributed VCO. ISSCC (2006)
Yolin Lih, Nestoras Tzartzanis, William W. Walker
A leakage current replica keeper for dynamic circuits. ISSCC (2006)
Hisashige Ando, Nestoras Tzartzanis, William W. Walker
A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing. IEEE Trans. Very Large Scale Integr. Syst. 13 (7) (2005)
Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. IEEE J. Solid State Circuits 40 (8) (2005)
Nestoras Tzartzanis, William W. Walker
Differential current-mode sensing for efficient on-chip global signaling. IEEE J. Solid State Circuits 40 (11) (2005)
Nestoras Tzartzanis, William W. Walker
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. ICCD (2003)
William C. Athas, Nestoras Tzartzanis, Weihua Mao, Lena Peterson, Rajat Lal, Kisup Chong, Joong-Seok Moon, Lars J. Svensson, Michael Bolotski
The design and implementation of a low-power clock-powered microprocessor. IEEE J. Solid State Circuits 35 (11) (2000)
Nestoras Tzartzanis, William C. Athas
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing. ARVLSI (1999)
Nestoras Tzartzanis, William C. Athas
Retractile clock-powered logic. ISLPED (1999)
William C. Athas, Nestoras Tzartzanis, Lars J. Svensson, Lena Peterson
A low-power microprocessor based on resonant energy. IEEE J. Solid State Circuits 32 (11) (1997)
William C. Athas, Nestoras Tzartzanis, Lars J. Svensson, Lena Peterson, Huimin Li, Xing Yu Jiang, Peiqing Wang, W.-C. Liu
AC-1: a clock-powered microprocessor. ISLPED (1997)
Nestoras Tzartzanis, William C. Athas
Energy recovery for the design of high-speed, low-power static RAMs. ISLPED (1996)
William C. Athas, Nestoras Tzartzanis
Energy recovery for low-power CMOS. ARVLSI (1995)
Nestoras Tzartzanis, William C. Athas
Design and analysis of a low-power energy-recovery adder. Great Lakes Symposium on VLSI (1995)
William C. Athas, Lars J. Svensson, Jefferey G. Koller, Nestoras Tzartzanis, E. Ying-Chin Chou
Low-power digital systems based on adiabatic-switching principles. IEEE Trans. Very Large Scale Integr. Syst. 2 (4) (1994)
Manolis Katevenis, Nestoras Tzartzanis
Reducing the Branch Penalty by Rearranging Instructions in Double-Width Memory. ASPLOS (1991)