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A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.

Kouichi KandaHirotaka TamuraTakuji YamamotoSatoshi MatsubaraMasaya KibuneYoshiyasu DoiTakayuki ShibasakiNestoras TzartzanisAnders KristenssonSamir ParikhSatoshi IdeYukito TsunodaTetsuji YamabanaMariko SugawaraNaoki KuwataTadashi IkeuchiJunji OgawaWilliam W. Walker
Published in: IEEE J. Solid State Circuits (2009)
Keyphrases
  • high speed
  • low cost
  • user friendly
  • user interface
  • neural network
  • data structure
  • low power
  • primal dual
  • power supply
  • cmos technology