A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS.
Yasumoto TomitaMasaya KibuneJunji OgawaWilliam W. WalkerHirotaka TamuraTadahiro KurodaPublished in: IEEE J. Solid State Circuits (2005)
Keyphrases
- high speed
- decision feedback
- intersymbol interference
- analog vlsi
- cmos technology
- spl times
- low cost
- circuit design
- low power
- cmos image sensor
- real time
- multipath
- single chip
- monitoring system
- computer simulation
- focal plane
- error propagation
- development environment
- image sensor
- power consumption
- data acquisition
- mixed signal
- social sciences
- soft decision
- parallel processing
- high density
- nm technology
- random access memory
- delay insensitive
- low power consumption
- dynamic range