Takayuki Kawahara

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 20

Top Topics

Health Monitoring

Gradient Vector

Fully Connected

Top Venues

Publications

Taichi Megumi, Akari Endo, Takayuki Kawahara
Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI. IEEE Access 12 (2024)
Yuya Hayakawa, Yuga Aoki, Kenjiro Mori, Takumi Ito, Takayuki Kawahara
Experimental Investigation of the Generalization Performance of Neural Network in Defect Localization System for Steel Pipe Health Monitoring. TENCON (2023)
Yuya Fujiwara, Takayuki Kawahara
BNN Training Algorithm with Ternary Gradients and BNN based on MRAM Array. TENCON (2023)
Akihiro Yamada, Yuwa Kishi, Takayuki Kawahara
Bi-directional read method to reduce SOT-specific read disturbance for highly reliable SOT-MRAM. IMW (2022)
Kaoru Yamamoto, Takayuki Kawahara
Scalable fully coupled annealing processing system and multi-chip FPGA implementation. Microprocess. Microsystems 95 (2022)
Yudai Taguchi, Ryoma Iimura, Takayuki Kawahara
FPGA Implementation of Support Vector Machine Using Ising Model for AI on Things. CIVEMSA (2021)
Ryoma Iimura, Satoshi Kitamura, Takayuki Kawahara
Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With 512 Fully Connected Spins. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (12) (2021)
Ryoma Iimura, Satoshi Kitamura, Takayuki Kawahara
Implementation of Multi Spin-Thread Architecture to Fully-Connected Annealing Processing AI Chips. MWSCAS (2020)
Kohei Koike, Kenta Suzuki, Mengnan Ke, Kenjiro Mori, Takumi Ito, Takayuki Kawahara
Damage-Position Identification of Wooden-House Models for Structural Health Monitoring Using Machine Learning. APCCAS (2020)
Ryoto Ono, Kenta Someya, Takayuki Kawahara
A novel Ising model processing achieving all interactions only by adjacent spins for a high-speed solver for versatile Ising machines. Microprocess. Microsystems 78 (2020)
Kenta Suzuki, Takumi Ito, Kohei Koike, Takayuki Kawahara, Mengnan Ke, Kenjiro Mori
Improvement of Generalization Performance for Timber Health Monitoring using Machine Learning. APCCAS (2020)
Akira Minamisawa, Ryoma Iimura, Takayuki Kawahara
High-speed Sparse Ising Model on FPGA. MWSCAS (2019)
Ryota Tanida, Jing Ma, Takashi Nakajima, Mikio Hasegawa, Takahiro Yamamoto, Takumi Ito, Takayuki Kawahara, Atsushi Yamamoto, Noriaki Takahashi, Natsuhiko Sakiyama, Sakuya Kishi, Takayuki Kishimoto, So Hasegawa, Kenjiro Mori, Yoichiro Hashizume
Machine Learning Classification Methods using Data of 3-axis Acceleration Sensors equipped with Wireless Communication Means for Locating Wooden House Structural Damage. APCCAS (2019)
Tatsuya Hiejima, Shun Kawashima, Mengnan Ke, Takayuki Kawahara
Effectiveness of Synchronization and Cooperative Behavior of Multiple Robots based on Swarm AI. APCCAS (2019)
Takumi Ito, Changhoon Choi, Takahiro Yamamoto, Takashi Nakajima, Takayuki Kawahara, Yoichiro Hashizume, Mikio Hasegawa
Live Demonstration of IoT and AI System for Recognition of States of Buildings subjected to Seismic Vibration Motion. ISCAS (2018)
Ryota Tanida, Ryo Oiwa, Takumi Ito, Takayuki Kawahara
Wooden Framed House Structural Health Monitoring by System Identification and Damage Detection under Dynamic Motion with Artificial Intelligence Sensor using a Model of House including Braces. CIVEMSA (2018)
Yasushi Fukuda, Zule Xu, Takayuki Kawahara
Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error. IEICE Trans. Electron. (12) (2017)
Ryo Oiwa, Takumi Ito, Takayuki Kawahara
Timber Health Monitoring using piezoelectric sensor and machine learning. CIVEMSA (2017)
Zule Xu, Takayuki Kawahara
A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design. IEICE Trans. Electron. (4) (2017)
Kenta Someya, Ryoto Ono, Takayuki Kawahara
Novel Ising model using dimension-control for high-speed solver for Ising machines. NEWCAS (2016)
H. Kazama, Takayuki Kawahara
STT-RAM read stability in DRAM operating region. NVMTS (2015)
Isamu Wakabayashi, Yuki Fukushima, Takayuki Kawahara
An eight-channel FDM system using Mach-Zehnder filters with cosine roll-off band-limiting characteristics. APSITT (2015)
Yuki Fukushima, Isamu Wakabayashi, Takayuki Kawahara
Equalization for the FDM System Using Mach-Zehnder Filters. AINA Workshops (2015)
Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara
What is a good way to expand a silicon value to a solution value? A-SSCC (2014)
Yoshimitsu Yanagawa, Naoshi Itabashi, Sonoko Migitaka, Takahide Yokoi, Makiko Yoshida, Takayuki Kawahara
On-chip base sequencing using a two-stage reaction-control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-based DNA sequencer. BioCAS (2013)
Takayuki Kawahara, Kenchi Ito, Riichiro Takemura, Hideo Ohno
Spin-transfer torque RAM technology: Review and prospect. Microelectron. Reliab. 52 (4) (2012)
Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device. IEICE Trans. Electron. (4) (2012)
Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device. ISCAS (2012)
Takayuki Kawahara
Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing. IEEE Des. Test Comput. 28 (1) (2011)
Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. IEEE J. Solid State Circuits 45 (4) (2010)
Masanao Yamaoka, Kenichi Osada, Takayuki Kawahara
A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. ESSCIRC (2008)
Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. IEEE J. Solid State Circuits 43 (1) (2008)
Takayuki Kawahara
Low-Voltage Embedded RAMs in Nanometer Era. IEICE Trans. Electron. (4) (2007)
Takayuki Kawahara, Riichiro Takemura, Hiromasa Takahashi, Hideo Ohno
SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. ICECS (2007)
Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. ISSCC (2007)
Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. ISSCC (2007)
Masanao Yamaoka, Takayuki Kawahara
Operating-margin-improved SRAM with column-at-a-time body-bias control technique. ESSCIRC (2007)
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara
Twin Cell for Sub 1-V Operation. IEICE Trans. Electron. (4) (2007)
Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ACM Great Lakes Symposium on VLSI (2007)
Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara
Ultra-low voltage nano-scale embedded RAMs. ISCAS (2006)
Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. IEEE J. Solid State Circuits 41 (1) (2006)
Masanao Yamaoka, Ryuta Tsuchiya, Takayuki Kawahara
SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors. IEEE J. Solid State Circuits 41 (11) (2006)
Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. IEEE J. Solid State Circuits 41 (3) (2006)
Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara
A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. ICC (2005)
Kenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa
Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. CICC (2005)
Goichi Ono, Masayuki Miyazaki, Kazuki Watanabe, Takayuki Kawahara
An LSI system with locked in temperature insensitive state achieved by using body bias technique. ISCAS (1) (2005)
Hideaki Kurata, Shunichi Saeki, Takashi Kobayashi, Yoshitaka Sasago, Tsuyoshi Arigane, Kazuo Otsuga, Takayuki Kawahara
Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories. IEEE J. Solid State Circuits 40 (2) (2005)
Masayuki Miyazaki, Goichi Ono, Takayuki Kawahara
Optimum threshold-voltage tuning for low-power, high-performance microprocessor. ISCAS (1) (2005)
Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. IEEE J. Solid State Circuits 40 (4) (2005)
Kenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara
Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. CICC (2004)
Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takayuki Kawahara
SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. IEEE J. Solid State Circuits 39 (5) (2004)
Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara
Low-Voltage Embedded RAMs - Current Status and Future Trends. PATMOS (2004)
Goichi Ono, Masayuki Miyazaki, Hidetoshi Tanaka, Nono Ohkubo, Takayuki Kawahara
Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption [ubiquitous computing processors]. ESSCIRC (2004)
Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara, Kiyoo Itoh
Review and future prospects of low-voltage RAM circuits. IBM J. Res. Dev. 47 (5-6) (2003)
Masayuki Miyazaki, Hidetoshi Tanaka, Goichi Ono, Tomohiro Nagano, Norio Ohkubo, Takayuki Kawahara, Kazuo Yano
Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment. ISLPED (2003)
Takayuki Kawahara, Syun-ichi Saeki, Yusuke Jyouno, Naoki Miyamoto, Takashi Kobayashi, Katsutaka Kimura
Internal voltage generator for low voltage, quarter-micrometer flash memories. IEEE J. Solid State Circuits 33 (1) (1998)
Takayuki Kawahara, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, Katsutaka Kimura
20-Mb/s erase/record flash memory by asymmetrical operation. IEEE J. Solid State Circuits 33 (1) (1998)
Takayuki Kawahara, Takashi Kobayashi, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, T. Adachi, Masataka Kato, Akihiko Sato, J. Yugami, Hitoshi Kume, Katsutaka Kimura
Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. IEEE J. Solid State Circuits 31 (11) (1996)
Takayuki Kawahara, Naoki Miyamoto, Syun-ichi Saeki, Yusuke Jyouno, Masataka Kato, Katsutaka Kimura
High reliability electron-ejection method for high density flash memories. IEEE J. Solid State Circuits 30 (12) (1995)