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90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique.

Masanao YamaokaNoriaki MaedaYoshihiro ShinozakiYasuhisa ShimazakiKoji NiiShigeru ShimadaKazumasa YanagisawaTakayuki Kawahara
Published in: IEEE J. Solid State Circuits (2006)
Keyphrases
  • power line
  • low voltage
  • power consumption
  • dynamic random access memory