Satoru Hanzawa

Publication Activity (10 Years)

Years Active: 2005-2012
Publications (10 Years): 0

Top Topics

Associative Memory

Information Systems

Top Venues

Publications

Tadaaki Yamauchi, Satoru Hanzawa
Session 25 overview: Non-volatile memory solutions: Memory subcommittee. ISSCC (2012)
Satoru Hanzawa, Takahiro Hanyu
Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device. IEICE Trans. Electron. (8) (2011)
Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. ISSCC (2007)
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara
Twin Cell for Sub 1-V Operation. IEICE Trans. Electron. (4) (2007)
Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. IEEE J. Solid State Circuits 41 (1) (2006)
Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara
A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. ICC (2005)
Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. IEEE J. Solid State Circuits 40 (4) (2005)