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Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.
Kiyoo Itoh
Masanao Yamaoka
Takayuki Kawahara
Published in:
ACM Great Lakes Symposium on VLSI (2007)
Keyphrases
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low voltage
cmos technology
random access memory
leakage current
low power
design considerations
power dissipation
power line
parallel processing
power consumption
silicon on insulator
high speed
low cost
power management
multiple views
moving objects
video sequences