Katsutaka Kimura

Publication Activity (10 Years)

Years Active: 1993-2002
Publications (10 Years): 0

Publications

Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura
A low-impedance open-bitline array for multigigabit DRAM. IEEE J. Solid State Circuits 37 (4) (2002)
Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh
open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. IEEE J. Solid State Circuits 36 (11) (2001)
Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. IEEE J. Solid State Circuits 34 (8) (1999)
Takayuki Kawahara, Syun-ichi Saeki, Yusuke Jyouno, Naoki Miyamoto, Takashi Kobayashi, Katsutaka Kimura
Internal voltage generator for low voltage, quarter-micrometer flash memories. IEEE J. Solid State Circuits 33 (1) (1998)
Takayuki Kawahara, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, Katsutaka Kimura
20-Mb/s erase/record flash memory by asymmetrical operation. IEEE J. Solid State Circuits 33 (1) (1998)
Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya
The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. IEEE J. Solid State Circuits 32 (5) (1997)
Takayuki Kawahara, Takashi Kobayashi, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, T. Adachi, Masataka Kato, Akihiko Sato, J. Yugami, Hitoshi Kume, Katsutaka Kimura
Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. IEEE J. Solid State Circuits 31 (11) (1996)
Takayuki Kawahara, Naoki Miyamoto, Syun-ichi Saeki, Yusuke Jyouno, Masataka Kato, Katsutaka Kimura
High reliability electron-ejection method for high density flash memories. IEEE J. Solid State Circuits 30 (12) (1995)
Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito
synapse neural network. IEEE Trans. Neural Networks 4 (3) (1993)