Hiroki Fujisawa

Publication Activity (10 Years)

Years Active: 1997-2007
Publications (10 Years): 0

Publications

Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. IEEE J. Solid State Circuits 42 (1) (2007)
Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. ISSCC (2006)
Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. IEEE J. Solid State Circuits 40 (4) (2005)
Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. IEEE J. Solid State Circuits 38 (5) (2003)
Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura
A low-impedance open-bitline array for multigigabit DRAM. IEEE J. Solid State Circuits 37 (4) (2002)
Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya
A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs. IEEE J. Solid State Circuits 36 (7) (2001)
Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh
open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. IEEE J. Solid State Circuits 36 (11) (2001)
Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya
The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. IEEE J. Solid State Circuits 32 (5) (1997)