Yasuhiro Takai

Publication Activity (10 Years)

Years Active: 1994-2013
Publications (10 Years): 0

Top Topics

International Conference

High Reliability

Computer Society

Hard Disk Drive

Top Venues

IEEE J. Solid State Circuits

Publications

Yasuhiro Takai, James Sung
Session 17 overview: High-performance DRAM interfaces. ISSCC (2013)
Maurits Ortmanns, Timothy Fischer, Uming Ko, Wim Dehaene, Yasuhiro Takai
Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 48 (1) (2013)
Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. IEEE J. Solid State Circuits 40 (4) (2005)
Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. IEEE J. Solid State Circuits 38 (5) (2003)
Yasuhiro Takai, Mamoru Fujita, Kyoichi Nagata, Satoshi Isa, Shigeyuki Nakazawa, Atsunori Hirobe, Hiroaki Ohkubo, Masato Sakao, Shinichi Horiba, Tadashi Fukase, Yoshihiro Takaishi, Makoto Matsuo, Masahiro Komuro, Tetsuya Uchida, Takashi Sakoh, Kanta Saino, Shirou Uchiyama, Yuichi Takada, Junichi Sekine, Nobuko Nakanishi, Takeshi Oikawa, Masahiko Igeta, Hiroyoshi Tanabe, Hidenobu Miyamoto, Takeo Hashimoto, Hiromu Yamaguchi, Kuniaki Koyama, Yasuo Kobayashi, Takashi Okuda
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme. IEEE J. Solid State Circuits 35 (2) (2000)
Yasuhiro Takai, Mamoru Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Yukio Fukuzo, Hiroshi Watanabe
250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture. IEEE J. Solid State Circuits 29 (4) (1994)