A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.
Tatsuya MatanoYasuhiro TakaiTsugio TakahashiYuusuke SakitoIsamu FujiiYoshihiro TakaishiHiroki FujisawaShuichi KubouchiSeiji NaruiKoji AraiMakoto MorinoMasayuki NakamuraShinichi MiyatakeToshihiro SekiguchiKuniaki KoyamaPublished in: IEEE J. Solid State Circuits (2003)