Masayuki Nakamura

Publication Activity (10 Years)

Years Active: 1996-2016
Publications (10 Years): 1

Top Topics

Resource Management

Top Venues

J. Robotics Mechatronics

Publications

Kohei Sugiyama, Takayuki Matsuno, Tetsushi Kamegawa, Takao Hiraki, Hirotaka Nakaya, Masayuki Nakamura, Akira Yanou, Mamoru Minami
Needle Tip Position Accuracy Evaluation Experiment for Puncture Robot in Remote Center Control. J. Robotics Mechatronics 28 (6) (2016)
Masayuki Nakamura, Takashi Yoshikawa, Kayo Tanaka, Mengyuan Liao, Noriaki Kuwahara
The Digital Reminiscence Method: Effect on Dementia in Japanese Day Care Centers. HCI (17) (2015)
Hideaki Hashimoto, Keigo Matsuo, Kazuaki Chikira, Masayuki Nakamura, Joji Urata
Energy-aware resource management of virtual machines under thermal and placement constraints. IGCC (2014)
Takayuki Nakamura, Yukio Kikuya, Yutaka Arakawa, Motonori Nakamura, Yuka Higashijima, Yasuko Yamada Maruo, Masayuki Nakamura
Proposal of Web Framework for Ubiquitous Sensor Network and Its Trial Application Using NO2 Sensor Mounted on Bicycle. SAINT (2012)
Masayuki Nakamura, Jiro Nakamura, Guillaume Lopez, Masaki Shuzo, Ichiro Yamada
Collaborative Processing of Wearable and Ambient Sensor System for Blood Pressure Monitoring. Sensors 11 (7) (2011)
Masayuki Nakamura, Atsushi Sakurai, Jiro Nakamura
Distributed Environment Control Using Wireless Sensor/Actuator Networks for Lighting Applications. Sensors 9 (11) (2009)
Masayuki Nakamura, Shoshin Kubota, Hideaki Takagi, Kiyoshi Einaga, Masashi Yokoyama, Katsuto Mochizuki, Masaomi Takizawa, Sumio Murase
Development of Long-Range and High-Speed Wireless LAN for the Transmission of Telemedicine from Disaster Areas. EURASIP J. Wirel. Commun. Netw. 2008 (2008)
Masayuki Nakamura, Atsushi Sakurai, Takumi Yamada, Jiro Nakamura
Adaptive sensor/actuator networks for tracking environment control behaviors. CSTST (2008)
Masayuki Nakamura, Atsushi Sakurai, Shizuo Furubo, Hiroshi Ban
Collaborative processing in Mote-based sensor/actuator networks for environment control application. Signal Process. 88 (7) (2008)
Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. IEEE J. Solid State Circuits 42 (1) (2007)
Masayuki Nakamura, Atsushi Sakurai, Toshio Watanabe, Jiro Nakamura, Hiroshi Ban
Improved Collaborative Environment Control Using Mote-based Sensor/Actuator Networks. LCN (2006)
Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. ISSCC (2006)
Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. IEEE J. Solid State Circuits 40 (4) (2005)
Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso
Is methodology the highway out of verification hell? DAC (2005)
Masayuki Nakamura, Hiroki Nomiya, Kuniaki Uehara
Improvement of Boosting Algorithm by Modifying the Weighting Rule. Ann. Math. Artif. Intell. 41 (1) (2004)
Masayuki Nakamura, Yuying Yang, Katsumi Wasaki, Yasunari Shidama
Study on a noise reduction system of CATV network upstream for data communication. ICCCN (2003)
Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. IEEE J. Solid State Circuits 38 (5) (2003)
Masayuki Nakamura, Kuniaki Uehara
Improvement of Boosting Algorithm by Modifying the Weighting Rule. AI&M (2002)
Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura
A low-impedance open-bitline array for multigigabit DRAM. IEEE J. Solid State Circuits 37 (4) (2002)
Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya
A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs. IEEE J. Solid State Circuits 36 (7) (2001)
Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh
open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. IEEE J. Solid State Circuits 36 (11) (2001)
Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato
A 29-ns 64-Mb DRAM with hierarchical array architecture. IEEE J. Solid State Circuits 31 (9) (1996)