Tadashi Tachibana

Publication Activity (10 Years)

Years Active: 1996-1999
Publications (10 Years): 0

Publications

Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. IEEE J. Solid State Circuits 34 (8) (1999)
Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register. IEEE J. Solid State Circuits 33 (2) (1998)
Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato
A 29-ns 64-Mb DRAM with hierarchical array architecture. IEEE J. Solid State Circuits 31 (9) (1996)