A 29-ns 64-Mb DRAM with hierarchical array architecture.
Masayuki NakamuraTugio TakahashiTakesada AkibaGoro KitsukawaMakoto MorinoToshihiro SekiguchiIsamu AsanoKatsuo KomatsuzakiYoshitaka TadakiSongsu ChoKazuhiko KajigayaTadashi TachibanaKatsuyuki SatoPublished in: IEEE J. Solid State Circuits (1996)