Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register.
Youji IdeiKatsuhiro ShimohigashiMasakazu AokiHiromasa NodaHidetoshi IwaiKatsuyuki SatoTadashi TachibanaPublished in: IEEE J. Solid State Circuits (1998)
Keyphrases
- low power
- high speed
- low cost
- cmos technology
- single chip
- mixed signal
- power consumption
- low power consumption
- low voltage
- vlsi architecture
- high density
- vlsi implementation
- ultra low power
- power dissipation
- image sensor
- nm technology
- signal processor
- high power
- digital signal processing
- vlsi circuits
- logic circuits
- gate array
- power reduction
- embedded dram
- real time
- main memory