1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.
Hiroki FujisawaMasayuki NakamuraYasuhiro TakaiYasuji KoshikawaTatsuya MatanoSeiji NaruiNarikazu UsukiChiaki DonoShinichi MiyatakeMakoto MorinoKoji AraiShuichi KubouchiIsamu FujiiHideyuki YokoTakao AdachiPublished in: IEEE J. Solid State Circuits (2005)