A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme.
Yasuhiro TakaiMamoru FujitaKyoichi NagataSatoshi IsaShigeyuki NakazawaAtsunori HirobeHiroaki OhkuboMasato SakaoShinichi HoribaTadashi FukaseYoshihiro TakaishiMakoto MatsuoMasahiro KomuroTetsuya UchidaTakashi SakohKanta SainoShirou UchiyamaYuichi TakadaJunichi SekineNobuko NakanishiTakeshi OikawaMasahiko IgetaHiroyoshi TanabeHidenobu MiyamotoTakeo HashimotoHiromu YamaguchiKuniaki KoyamaYasuo KobayashiTakashi OkudaPublished in: IEEE J. Solid State Circuits (2000)