250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture.
Yasuhiro TakaiMamoru NagaseMamoru KitamuraYasuji KoshikawaNaoyuki YoshidaYasuaki KobayashiTakashi ObaraYukio FukuzoHiroshi WatanabePublished in: IEEE J. Solid State Circuits (1994)