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250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture.

Yasuhiro TakaiMamoru NagaseMamoru KitamuraYasuji KoshikawaNaoyuki YoshidaYasuaki KobayashiTakashi ObaraYukio FukuzoHiroshi Watanabe
Published in: IEEE J. Solid State Circuits (1994)
Keyphrases
  • pipelined architecture
  • hardware implementation
  • high density
  • asynchronous communication
  • main memory
  • cooperative
  • multi agent systems
  • distributed systems
  • low voltage