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A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS.
Yanfei Chen
Sanroku Tsukamoto
Tadahiro Kuroda
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2010)
Keyphrases
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power consumption
analog to digital converter
power supply
nm technology
high speed
hd video
random access memory
real time
low cost
higher level
sar images
multiresolution
low power