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A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation.
Hyunui Lee
Yusuke Asada
Masaya Miyahara
Akira Matsuzawa
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2013)
Keyphrases
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power consumption
analog to digital converter
image interpolation
nm technology
weighted sum
pattern matching
interpolation method
multiple input