One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise.
Toru NakuraYuki OkamotoYoshio MitaKunihiro AsadaPublished in: EWME (2016)
Keyphrases
- gate array
- low power
- analog vlsi
- mixed signal
- circuit design
- power consumption
- vlsi architecture
- low cost
- high speed
- cmos image sensor
- image sensor
- learning technologies
- cmos technology
- single chip
- floating gate
- logic circuits
- focal plane
- power dissipation
- e learning
- power supply
- educational technology
- multimedia
- delay insensitive
- serious games