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A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology.
Toru Nakura
Kimio Ueda
Kazuo Kubo
Yoshio Matsuda
Koichiro Mashiko
Tsutomu Yoshihara
Published in:
IEEE J. Solid State Circuits (2000)
Keyphrases
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cmos technology
power consumption
silicon on insulator
low power
power dissipation
spl times
low voltage
high speed
power management
mixed signal
parallel processing
digital signal processing
computer vision
low cost
multi view
video coding