A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator.
Takaaki ItoTetsuya IizukaToru NakuraKunihiro AsadaPublished in: ICECS (2017)
Keyphrases
- non binary
- analog to digital converter
- binary representation
- constraint satisfaction problems
- random access memory
- image sensor
- noise level
- missing data
- image reconstruction
- power consumption
- arc consistency
- synthetic aperture radar
- signal to noise ratio
- frequent pattern mining
- multi dimensional
- high speed
- sar images
- data streams
- constraint satisfaction
- small number
- state space
- knowledge discovery