Katsunori Tanaka

Publication Activity (10 Years)

Years Active: 2004-2009
Publications (10 Years): 0

Publications

Toru Yazawa, Katsunori Tanaka, Tomoo Katsuyama
Alternans Lowers the Scaling Exponent of Heartbeat Fluctuation Dynamics: A Detrended Fluctuation Analysis in Animal Models and Humans. CSIE (1) (2009)
Katsunori Tanaka, Yuichi Nakamura, Atsushi Atarashi
A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools. IPSJ Trans. Syst. LSI Des. Methodol. 1 (2008)
Katsunori Tanaka, Yuichi Nakamura, Atsushi Atarashi
A Study of Multi-core Processor Design with Asynchronous Interconnect Using Synchronous Design Tools. Inf. Media Technol. 3 (4) (2008)
Toru Yazawa, Katsunori Tanaka, Tomoo Katsuyama
Detrended Fluctuation Analysis of Heartbeat Interval Signal: Alternans Lowers the Scaling Exponent of Heartbeat Fluctuation Dynamics in Animal Models and Humans. BMEI (2) (2008)
Kohei Hosokawa, Katsunori Tanaka, Yuichi Nakamura
Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi
A transduction-based framework to synthesize RSFQ circuits. ASP-DAC (2006)
Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi
SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)
Katsunori Tanaka, Yahiko Kambayashi
Transduction method for design of logic cell structure. ASP-DAC (2004)
Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi
SPFD-based one-to-many rewiring. FPGA (2004)
Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi
SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits. ACM Great Lakes Symposium on VLSI (2004)