Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs.
Kohei HosokawaKatsunori TanakaYuichi NakamuraPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2007)
Keyphrases
- high speed
- hardware implementation
- limited memory
- low cost
- hardware and software
- real time
- computing power
- hardware architecture
- hardware design
- parallel architectures
- low power
- computational power
- memory usage
- computing systems
- internal memory
- memory space
- field programmable gate array
- massively parallel
- virtual machine
- embedded systems
- lightweight
- data processing
- neural network