​
Login / Signup
Susumu Imaoka
Publication Activity (10 Years)
Years Active: 2004-2009
Publications (10 Years): 0
</>
Publications
</>
Koji Nii
,
Yasumasa Tsukamoto
,
Makoto Yabuuchi
,
Yasuhiro Masuda
,
Susumu Imaoka
,
Keiichi Usui
,
Shigeki Ohbayashi
,
Hiroshi Makino
,
Hirofumi Shinohara
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access.
IEEE J. Solid State Circuits
44 (3) (2009)
Shigeki Ohbayashi
,
Makoto Yabuuchi
,
Kazushi Kono
,
Yuji Oda
,
Susumu Imaoka
,
Keiichi Usui
,
Toshiaki Yonezu
,
Takeshi Iwamoto
,
Koji Nii
,
Yasumasa Tsukamoto
,
Masashi Arakawa
,
Takahiro Uchida
,
Masakazu Okada
,
Atsushi Ishii
,
Tsutomu Yoshihara
,
Hiroshi Makino
,
Koichiro Ishibashi
,
Hirofumi Shinohara
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die.
IEEE J. Solid State Circuits
43 (1) (2008)
Koji Nii
,
Makoto Yabuuchi
,
Yasumasa Tsukamoto
,
Shigeki Ohbayashi
,
Susumu Imaoka
,
Hiroshi Makino
,
Yoshinobu Yamagami
,
Satoshi Ishikura
,
Toshio Terano
,
Toshiyuki Oashi
,
Keiji Hashimoto
,
Akio Sebe
,
Gen Okazaki
,
Katsuji Satomi
,
Hironori Akamatsu
,
Hirofumi Shinohara
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.
IEEE J. Solid State Circuits
43 (1) (2008)
Shigeki Ohbayashi
,
Makoto Yabuuchi
,
Kazushi Kono
,
Yuji Oda
,
Susumu Imaoka
,
Keiichi Usui
,
Toshiaki Yonezu
,
Takeshi Iwamoto
,
Koji Nii
,
Yasumasa Tsukamoto
,
Masashi Arakawa
,
Takahiro Uchida
,
Masakazu Okada
,
Atsushi Ishii
,
Hiroshi Makino
,
Koichiro Ishibashi
,
Hirofumi Shinohara
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.
ISSCC
(2007)
Shigeki Ohbayashi
,
Makoto Yabuuchi
,
Koji Nii
,
Yasumasa Tsukamoto
,
Susumu Imaoka
,
Yuji Oda
,
Tsutomu Yoshihara
,
Motoshige Igarashi
,
Masahiko Takeuchi
,
Hiroshi Kawashima
,
Yasuo Yamaguchi
,
Kazuhiro Tsukamoto
,
Masahide Inuishi
,
Hiroshi Makino
,
Koichiro Ishibashi
,
Hirofumi Shinohara
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.
IEEE J. Solid State Circuits
42 (4) (2007)
Makoto Yabuuchi
,
Koji Nii
,
Yasumasa Tsukamoto
,
Shigeki Ohbayashi
,
Susumu Imaoka
,
Hiroshi Makino
,
Yoshinobu Yamagami
,
Satoshi Ishikura
,
Toshio Terano
,
Toshiyuki Oashi
,
Keiji Hashimoto
,
Akio Sebe
,
Gen Okazaki
,
Katsuji Satomi
,
Hironori Akamatsu
,
Hirofumi Shinohara
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.
ISSCC
(2007)
Yasumasa Tsukamoto
,
Koji Nii
,
Susumu Imaoka
,
Yuji Oda
,
Shigeki Ohbayashi
,
Tomoaki Yoshizawa
,
Hiroshi Makino
,
Koichiro Ishibashi
,
Hirofumi Shinohara
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability.
ICCAD
(2005)
Koji Nii
,
Yasumasa Tsukamoto
,
Tomoaki Yoshizawa
,
Susumu Imaoka
,
Yoshinobu Yamagami
,
Toshikazu Suzuki
,
Akinori Shibayama
,
Hiroshi Makino
,
Shuhei Iwade
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications.
IEEE J. Solid State Circuits
39 (4) (2004)