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A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits.

Shigeki OhbayashiMakoto YabuuchiKoji NiiYasumasa TsukamotoSusumu ImaokaYuji OdaTsutomu YoshiharaMotoshige IgarashiMasahiko TakeuchiHiroshi KawashimaYasuo YamaguchiKazuhiro TsukamotoMasahide InuishiHiroshi MakinoKoichiro IshibashiHirofumi Shinohara
Published in: IEEE J. Solid State Circuits (2007)
Keyphrases
  • low power
  • cmos technology
  • embedded systems
  • dynamic random access memory
  • power reduction
  • power consumption
  • random access memory
  • high speed
  • read write
  • low cost
  • logic synthesis
  • write operations