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A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.

Koji NiiMakoto YabuuchiYasumasa TsukamotoShigeki OhbayashiSusumu ImaokaHiroshi MakinoYoshinobu YamagamiSatoshi IshikuraToshio TeranoToshiyuki OashiKeiji HashimotoAkio SebeGen OkazakiKatsuji SatomiHironori AkamatsuHirofumi Shinohara
Published in: IEEE J. Solid State Circuits (2008)
Keyphrases
  • power consumption
  • data sets
  • process model
  • cmos technology