Yoshinobu Yamagami

Publication Activity (10 Years)

Years Active: 2004-2008
Publications (10 Years): 0

Publications

Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. IEEE J. Solid State Circuits 43 (4) (2008)
Toshikazu Suzuki, Hiroyuki Yamauchi, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu
A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. IEEE J. Solid State Circuits 43 (9) (2008)
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. IEEE J. Solid State Circuits 43 (1) (2008)
Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami
A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Trans. Electron. (4) (2007)
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. ISSCC (2007)
Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. IEEE J. Solid State Circuits 41 (1) (2006)
Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami
) Variation. IEICE Trans. Electron. (11) (2006)
Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi
0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. IEICE Trans. Electron. (4) (2005)
Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. IEEE J. Solid State Circuits 39 (4) (2004)